1. Field of the Invention
The present invention relates to a pulse generation circuit, and particularly, to a pulse generation circuit of a memory.
2. Description of the Related Art
As shown in FIG. 1, a conventional static RAM circuit includes a read/write control unit 1 provided for outputting first and second control signals CS and WE so as to control a read/write operation in a static RAM circuit in accordance with a chip selection signal CSB, a write enable signal WEB and an output enable signal OEB, an address input unit 2 provided for outputting signals ADS0 and ADS1 each corresponding to first and second address signals AD0 and AD1, respectively, which are applied from an externally connected element by a first control signal CS outputted from the read/write control unit 1, a data input unit 3 provided for outputting data corresponding to data DATA IN outputted from an externally connected element in accordance with a second control signal outputted from the read/write control unit 1, an address decoding unit 4 provided for decoding signals ADS0 and ADS1 outputted from the address input unit 2, an address transition detector 5 provided for detecting the transition of the signals ADS0 and ADS1 outputted from the address input unit 2 and for outputting an address transition detection pulse ATP, a pulse generator 6 provided for outputting a word line enable signal WLE and a sense amplifying enable signal SAE in accordance with an address transition detection signal ATF outputted from the address transition detectors, a logic operator 7 provided for logically operating a signal outputted from the address decoding unit 4 and a word line enable signal WLE outputted from the pulse generator 6, a data transfer unit 9 provided for transferring the data stored in a memory cell 8 to bit lines BL and BLB and for transferring the data outputted from the data input unit 3 to the memory cell 8 through the bit lines BL and BLB after it is enabled by a sense amplifying enable signal SAE outputted from the pulse generator 6, a sense amplifier 10 provided for amplifying the data outputted from the data transfer unit 9 after it is enabled by a sense amplifying enable signal SAE outputted from the pulse generator 6, and an output buffer 11 provided for buffering the data SAO and SAOB outputted from the sense amplifier 10 and for outputting the buffered data DATA OUT.
The address decoding unit 4 includes inverters I1 and I2 provided for inverting the signals ADS0 and ADS1 outputted from the address input unit 2, an AND gate A1 provided for logically ANDing the signals outputted from the inverters I1 and I2, an AND gate A2 provided for ANDing the signal outputted from the inverter I1 and the signal ADS1 outputted from the address input unit 2, an AND gate A3 provided for ANDing the signal ADS0 outputted from the address input unit 2 and the signal outputted from the inverter I2, and an AND gate A4 provided for ANDing the signals ADS0 and ADS1 outputted from the address input unit 2.
The address transition detector 5 includes first and second address transition detectors 5a and 5b, respectively, for detecting the transition of the signals ADS0 and ADS1 outputted from the address input unit 2 and for outputting the address transition detection pulses ATP0 and ATP1, and an OR gate 5c provided for ORing the address transition detection pulses ATP0 and ATP1 outputted from the first and second address transition detectors 5a and 5b, respectively, and for outputting the address transition detection pulse ATP.
The logic operator 7 includes AND gates A5, A6, A7, and A8 each of which provides for ANDing the signal outputted from AND gates A1, A2, A3, and A4, respectively, of the address decoding unit 4 and the word line enable signal WLE outputted from the pulse generator 6.
The operation of the conventional static RAM circuit will now be explained with reference to FIG. 2.
To begin with, when an address is designated to readout data stored in the memory cell 8, as shown in FIGS. 2A through 2C, a chip selection signal CSB of a low level signal, an enable signal WEB of a writing high level signal, and an output enable signal OEB of a low level signal are applied to the read/write control unit 1, respectively, from the outside of the static RAM circuit.
Thereafter, the read/write control unit 1 recognizes the operational state of the static RAM as a read cycle in accordance with the signals CSB, WEB, and OEB applied thereto and applies a first control signal CS of a high level signal to the address input unit 2, and applies a second control signal WE of a low level signal to the data input unit 3.
The first control signal CS is an inverting signal of the chip selection signal CSB applied to the read/write control unit 1, and the second control signal WE is an inverting signal of the enable signal WEB applied to the read/write control unit 1.
Thereafter, the data input unit 3 is disabled by the second control unit WE of a low level signal outputted from the read/write control unit 1.
Meanwhile, as the first control signal CS of a high level signal is applied to the address input unit 2 from the read/write control unit 1, the address input unit 2 is enabled and receives first and second address signals ADO and AD1 shown in FIGS. 2D and 2E, respectively, and outputs the signals ADS0 and ADS1 corresponding to the first and the second address signals AD0 and AD1.
The address decoding unit 4 decodes the signals ADS0 and ADS1 outputted from the address input unit 2. That is, the inverter I1 inverts the signal ADS0 and the inverter I2 inverts the signal ADS1.
The AND gate A1 ANDs the signals outputted from the inverters I1 and I2 and applies the ANDed signals to one terminal of the AND gate A5 of the logic operation unit 7. The AND gate A2 ANDs the signal outputted from the inverter I1 and the signal ADS1 and applies the ANDed signals to one terminal of the AND gate A6.
In addition, the AND gate A3 ANDs the signal outputted from the inverter I2 and the signal ADS0 and applies the ANDed signal to the AND gate A7. The AND gate A4 ANDs the signals ADS0 and ADS1 and applies the ANDed signal to one terminal of the AND gate A8 in the logic operation unit 7.
Meanwhile, in the address transition detection unit 5, the first and second address transition detection units 5a and 5b, as shown in FIGS. 2F and 2G, respectively, receive the signals ADS0 and ADS1 and detect the transitions of the signals ADS0 and ADS1, and apply the address transition detection pulses ATP0 and ATP1 of a low level signal to the AND gate 5c. Thereafter, the AND gate 5c, as shown in FIG. 2I, ANDs the address transition detection pulses ATP0 and ATP1 of a low level signal each outputted from the first and second address transition detection units 5a and 5b and applies the address transition detection signal ATP of a low level signal to the pulse generation unit 6.
The pulse generation unit 6, as shown in FIG. 2J, detects a descending point of the address transition detection pulse ATP of a low level signal outputted from the AND gate 5c and generates the word line enable signal WLE of a low level signal and outputs the word line enable signal WLE of a high level signal. In addition, the pulse generation unit 6, as shown in FIG. 2K, detects an ascending point of the address transition detection signal ATP outputted from the AND gate 5c and generates the sense amplifying enable signal SAE of a low level signal and applies the sense amplifying enable signal SAE of a high level signal to the data transmission unit 9 and the sense amplifier 10, respectively. Therefore, the sense amplifying enable signal SAE of a low level signal is generated after a predetermined time T after a word line enable signal WLE of a high level signal is generated.
Meanwhile, in the logic operation unit 7, the AND gates A5, A6, A7, and A8 receive the signals outputted from the AND gates A1, A2, A3, and A4, respectively, of the address decoding unit 4 and also receive and logically operate the word line enable signal WLE outputted from the pulse generation unit 6 and outputs the logically operated data. In addition, one word line out of the word lines is enabled by a result of the above described logic operation. In FIG. 1, there is shown one occasion that a word line WL is enabled by the signal outputted from the AND gate A5. That is, as shown in FIG. 2L, the word line WL becomes a high level signal when a word line enable signal WLE is a high level signal. At this time, the reason that there is shown a dotted line is because when a word line WL is enabled, an undesired word line is instantly enabled since the address signals ADO and AD1 are inputted with a predetermined delay time. Therefore, the data stored in the memory cell 8 is applied to the data transmission unit 9 through the bit lines BL and BLB, as shown in FIG. 2M.
Thereafter, the data transmission unit 9 is enabled by the sense amplifying enable signal SAE of a low level signal and applies the data, outputted from the bit lines BL and BLB, to the sense amplifier 10. The sense amplifier 10 is enabled by the sense amplifying enable signal SAE of a low level signal outputted from the pulse generation unit 6 and amplifies the data outputted from the data transmission unit 9 by a predetermined level and applies the amplified data SAO and SAOB to the output buffer 11, as shown in FIG. 2N. The output buffer 11 stores the data SAO and SAOB outputted from the sense amplifier 10 and at the same time outputs the data SAO and SAOB--DATA OUT.
Meanwhile, in order to store desired data into the memory cell 8, when a certain address is designated, a chip selection signal CSB, a write enable signal WEB, and an output enable signal OEB outputted from the outside of the static RAM for a predetermined time T1+T2+T3 are applied to the read/write control unit 1. When a chip selection signal CSB of high and low level signals, a write enable signal WEB of a high level signal, an output enable signal OEB of a high level signal for a predetermined time T1 are applied to the read/write control unit 1, the write/read control unit 1 recognizes the signal applied thereto as a read cycle by the signals CSB, WEB, and OEB and outputs the first control signal CS of a high level signal and the second control signal WE of a low level signal. The operation of the static RAM for a predetermined time T1 is the same as the operation of the read cycle described above and, therefore, a description of that operation is omitted.
When a chip selection signal CSB of a low level signal, an enable signal WEB of a low level signal, and an output enable signal OEB of a high level signal for a predetermined time T2 is applied to the read/write control unit 1, respectively, the read/write control unit 1 recognizes the signals applied thereto as a write cycle in accordance with the signals CSB, WEB, and OEB and applies the first control signal CS of a high level signal to the address input unit 2 and applies the second control signal WE of a high level signal to the data input unit 3. As the first control signal CS of a high level signal is applied to the address input unit 2, the description of the operations of the address input unit 2, the address decoding unit 4, and the address transition detection unit 5 is omitted because the operations thereof are the same as the read cycle.
Meanwhile, the pulse generation unit 6, as shown in FIGS. 2J and 2K, applies the word line enable signal WLE of a high level signal t the logic operation unit 7 and applies the sense enable signal SAE of a high level signal to the data transmission unit 10. Also, the data input unit 3 is enabled by the second control signal WE of a high level signal outputted from the read/write control unit 1 and applies the data corresponding to the externally applied data DATA IN to the data transmission unit 9. The data transmission unit 9 is enabled by a sense amplifying enable signal SAE of a high level signal outputted from the pulse generation unit 6 and stores the data outputted from the data input unit 9 into the memory cell 8 through the bit lines BL and BLB. Meanwhile, in a write cycle for a predetermined time T3, a chip selection signal CSB of low and high level signals, a write enable signal WEB of a high level signal, and an output enable signal OEB of a high level signal are applied to the read/write control unit 1, respectively. The read/write control unit 1 recognizes the signals applied thereto as a read cycle.
In the conventional static RAM circuit, since an address enable signal is generated at a descending point on a line of the address transition detection signal in a read cycle and since a sense amplifying enable signal is generated at an ascending point of the address transition detection signal, there are disadvantages in that the word line enable point and the sense amplifying enable point are delayed by a predetermined time T, so that the access time to the data stored in the memory cell is delayed. In addition, the word line enable points of the read cycle and the write cycle are the same, and an address cycle changes in a relation between the write enable signal and the address signal, and a writing operation is performed in an undesired address when a word line is enabled by a new address signal when a write enable signal changes to a read cycle.